1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a driving method that is adaptive for preventing a phenomenon causing a non-uniform charge characteristic between liquid crystal cells.
2. Description of the Related Art
A typical liquid crystal display (LCD) controls light transmittance of a liquid crystal having a dielectric anisotropy property using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type, and a driver for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines cross each other and liquid crystal cells are positioned at pixel areas defined by the crossings between the gate lines and the data lines. A pixel electrode and a common electrode are provided in each liquid crystal cell for applying an electric field to the liquid crystal cells. Each pixel electrode is connected to one of the data lines via source and drain terminals of a thin film transistor (TFT) provided as a switching device in each liquid crystal cell. A gate terminal of the TFT is connected to one of the gate lines. The gate lines are supplied with a scanning pulse.
The driver includes a gate driver for applying a scanning pulse or gate pulse to the gate lines; a data driver for converting a digital video data into an analog data voltage to supply it to the data lines; a timing controller for controlling the gate driver and the data driver; and a power supply for supplying various driving voltages used for the liquid crystal display device. The timing controller controls driving timing of the gate driver and the data driver, and supplies a digital video data to the data driver. The power supply uses a DC-DC converter to generate driving voltages to be supplied to the liquid crystal display panel including a common voltage Vcom, a gate high voltage VGH, and a gate low voltage VGL.
As liquid crystal display devices have trended towards large screens and high resolutions, the number of data lines and the number of gate lines of the liquid crystal display devices have increased. However, the liquid crystal display device has a problem in that, when the number of gate lines and data lines is increased, the number of data drivers and gate drivers is also increased accordingly.
In order to reduce the number of data drivers, liquid crystal display panels have been proposed in which adjacent liquid crystal cells can share a single data line to thereby reduce the number of data lines by half. FIG. 1 schematically illustrates a liquid crystal display panel having shared data lines, and FIG. 2 is a waveform diagram showing driving signals in the liquid crystal display panel shown in FIG. 1.
Referring to FIG. 1, the liquid crystal display panel of the related art having a shared data line structure includes liquid crystal cells 10 and 20 independently selected by different scanning pulses supplied from different gate lines GL1 to GLn to make a time divisional charge of data to the liquid crystal cells 10 and 20 from a single one of the data lines DL1 to DLm.
The first liquid crystal cells 10 arranged at the odd column each includes a first TFT 14 connected to one of the odd gate lines GL1, GL3 . . . GLn−1 and to the left side of one of the data lines DL1 to DLm, and a first pixel electrode 12 at the odd column connected to the first TFT 14. A source electrode of the first TFT 14 is connected to the left side of the data line DL while a drain electrode thereof is connected to the first pixel electrode 12. Further, a gate electrode of the TFT 14 is connected to odd gate lines GL1, GL3 . . . GLn−1.
The second liquid crystal cells 20 arranged at the even column each includes a second TFT 24 connected to one of the even gate lines GL2, GL4 . . . GLn and to the right side of one of the data lines DL1 to DLm, and a second pixel electrode 22 at the even column connected to the second TFT 24. A source electrode of the second TFT 24 is connected to the right side of the data line DL while a drain electrode thereof is connected to the second pixel electrode 22. Further, a gate electrode of the second TFT 24 is connected to the even gate lines GL2, GL4 . . . GLn.
Odd gate pulses for maintaining a high logic value TFT-on voltage during one horizontal period are sequentially applied to the odd gate lines GL1, GL3 . . . GLn−1 by means of the first gate driver. Even gate pulses for maintaining a high logic value TFT-on voltage during one horizontal period are sequentially applied to the even gate lines GL2, GL4 . . . GLn by means of the second gate driver. No period of overlap exists between the odd gate pulses and between the even gate pulses, whereas an overlapped period corresponding to ½ horizontal period exists between adjacent odd gate pulses and even gate pulses.
When a data voltage is supplied to the liquid crystal display panel as shown in FIG. 1 using a line inversion system, then charge characteristics between odd horizontal lines and even horizontal lines become different as shown in FIG. 2. The data driver has a line inversion system to invert the polarity of data for each horizontal line to supply them to the liquid crystal cells. In FIG. 1 and FIG. 2, ‘RO’, ‘BO’ and ‘GE’ represent red, green and blue liquid crystal cells at the odd column, and ‘GO’, ‘RE’ and ‘BE’ represent red, green and blue liquid crystal cells at the even column. Further, ‘SOE’ represents a source output enable signal for instructing a data output of the data driver. The data driver supplies a data voltage to the data lines DL1 to DLm during an interval between a falling edge and a rising edge of the SOE signal.
An operation of the liquid crystal display panel shown in FIG. 1 will be described below in which a negative data voltage is charged into the liquid crystal cells arranged at the odd horizontal lines while a positive data voltage is charged into the liquid crystal cells arranged at the even horizontal lines during an odd or even frame interval.
Referring to FIG. 1 and FIG. 2, first and second gate pulses which are overlapped for ½ horizontal period are sequentially applied to the first and second gate lines GL1 and GL2 for the purpose of charging a negative data into the liquid crystal cells included in the odd horizontal lines. The liquid crystal cells RO, BO and GE at the odd column included in the first horizontal line pre-charges a positive voltage by the last data voltage at the previous frame interval during the first half period of the first gate pulse, and thereafter charges negative data voltages −RO, −BO and −GE to be displayed during a P1 interval corresponding to the second half period of the first gate pulse and the first half period of the second gate pulse. During the P1 interval, the liquid crystal cells GO, RE and BE at the even column included in the first horizontal line pre-charge negative data voltages −RO, −BO and −GE. The liquid crystal cells GO, RE and BE at the even column included in the first horizontal line in which the negative voltage has been pre-charged during the P1 interval in this manner, charges negative data voltages −GO, −RE and −BE to be displayed during a P2 interval corresponding to the second half period of the second gate pulse.
Subsequently, third and fourth gate pulses, which are overlapped for ½ horizontal period are sequentially applied to the third and fourth gate lines GL3 and GL4 for the purpose of charging a positive data into the liquid crystal cells included in the even horizontal lines. The liquid crystal cells RO, BO and GE at the odd column included in the second horizontal line pre-charge negative voltages −GO, −RE and −BE during the P2 interval corresponding to the second half period of the second gate pulse and the first half period of the third gate pulse, and thereafter charges positive data voltages +RO, +BO and +GE during a P3 interval corresponding to the second half period of the third gate pulse. During the P3 interval, the liquid crystal cells GO, RE and BE at the even column included in the second horizontal line pre-charge positive data voltages +RO, +BO and +GE. The liquid crystal cells GO, RE and BE at the even column included in the second horizontal line in which a positive voltage has been pre-charged during the P3 interval in this manner, charge positive data voltages +GO, +RE and +BE to be displayed during a P4 interval corresponding to the second half period of the fourth gate pulse.
As a result, since the liquid crystal cells at the odd column and the liquid crystal cells at the even column in the liquid crystal display device as shown in FIG. 1 and FIG. 2 share the same data line, the liquid crystal display panel makes a time divisional application of a data voltage supplied via the same data line to the liquid crystal cells at the odd column and the liquid crystal cells at the even column, and pre-charges the liquid crystal cells at the next horizontal line into a data voltage at the previous horizontal line in order to heighten a charge speed of the liquid crystal cells.
In the liquid crystal display device as shown in FIG. 1 and FIG. 2, the liquid crystal cells at the odd column pre-charge positive voltages (or negative voltages) by the odd gate pulses and thereafter charge negative data voltages (or positive data voltages) to be displayed; whereas the liquid crystal cells at the even column pre-charge negative voltages (or positive voltages) by the even gate pulses and thereafter charge negative data voltages (or positive data voltages) to be displayed. In other words, the liquid crystal cells at the odd column charge a data voltage having a polarity different from the pre-charged voltage, whereas the liquid crystal cells at the even column charge a data voltage having the same polarity as the pre-charged voltage. Therefore, even when the liquid crystal display device shown in FIG. 1 and FIG. 2 supplies voltages having the same gray level to the liquid crystal cells at the odd column and the liquid crystal cells at the even column, a vertical stripe is generated on the display because voltages charged in the liquid crystal cells at the even column are relatively larger than voltages charged in the liquid crystal cells at the odd column.